Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training

National Science Foundation (NSF)

Note: This grant page has been archived and is very likely out of date.

Deadline: The deadline for this grant has passed

Grant amount: Up to US $10,000,000

Fields of work: Computer Science & Engineering Electrical Engineering

Applicant type: Nonprofit, College / University

Funding uses: Project / Program, Research

Location of project: United States

Location of residency: United States

Overview:

NOTE: All applications are due by 5:00 PM local time of applicant organization.

Integrated micro/nano-electronic circuits (ICs) are a foundational technology that enable advancements in artificial intelligence, 5G/6G communication, security, scientific computing, quantum computing, and more. The economic competitiveness, technological leadership, and national security of the United States depend on a future workforce at the forefront of IC design and fabrication, spanning IC researchers, IC designers, and IC fabrication engineers and technicians. Since IC design and fabrication must deal with staggering complexities to meet system functionality, performance, and energy objectives, offering students at all levels with hands-on experiences designing and fabricating IC chips is imperative. The needs of research and education communities in this domain have been widely recognized by a range of reports, including those derived from NSF-sponsored workshops.

The aim of this solicitation is 

  • to dramatically lower the barriers to accessing state-of-the-art electronic design automation (EDA) tools,
  • process design kits (PDKs), and design intellectual property (IP) cores for students and academic researchers, and
  • to enable students at various levels to design IC chips.

A key goal is to broaden participation in IC chip design beyond the small number of institutions currently engaged in these activities. This solicitation seeks proposals to establish and manage a community infrastructure that supports the entire IC chip design process beginning from behavior/structural description at the Register Transfer Level (RTL) or above to GDSII fabrication mask file generation. 

We've imported the main document for this grant to give you an overview. You can learn more about this opportunity by visiting the funder's website.

National Science Foundation (NSF)
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This page was last reviewed February 26, 2024 and last updated February 26, 2024